1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
In some applications, fins for FinFET devices are formed such that the fin is vertically spaced apart from and above the substrate with an isolation material positioned between the fin and the substrate. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 15 at an intermediate point during fabrication. In this example, the FinFET device 10 includes three illustrative fins 20, an isolation region 25 formed in trenches between the fins 20, a gate structure 30 formed above the fins 20, sidewall spacers 35 formed on sidewalls of the gate structure 30, and a gate cap layer 40 formed on a top surface of the gate structure 30. The fins 20 have a three-dimensional configuration: a height, a width and an axial length. The portions of the fins 20 covered by the gate structure 30 are the channel regions of the FinFET device 10, while the portions of the fins 20 positioned laterally outside of the spacers 35 are part of the source/drain regions of the FinFET device 10. Although not depicted, the portions of the fins 20 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
FIG. 1B is a cross-sectional view of an illustrative integrated circuit product 100 including a transistor device 105 formed in and above a semiconductor substrate 110. In the depicted example, the transistor device 105 includes an illustrative gate structure, i.e., a gate insulation layer 115 and a gate electrode 120, a gate cap layer 125, a sidewall spacer 130 and simplistically depicted source/drain regions 135. Although a planar device is illustrated, the discussion is also applicable to a FinFET device, such as the device 10 of FIG. 1A. At the point of fabrication depicted in FIG. 1B, layers of insulating material 135, 140, i.e., interlayer dielectric materials, have been formed above the product 100. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. A source/drain contact structure 140 connects to the source/drain region 135, referred to as a “CA” contact, and a gate contact structure 145 connects to the gate electrode 120, referred to as a “CB” contact. Also depicted in FIG. 1B is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 100 that is formed in the layer of insulating material 140, e.g., a low-k insulating material. A plurality of conductive vias—so-called V0 vias 150—are provided to establish electrical connection between the device-level contacts—the CA contact 140 and the CB contact 145—and the M1 layer. The M1 layer typically includes a plurality of metal lines 155 that are routed as needed across the product 100.
To prevent dielectric breakdown and a resulting short between the CA contact 140 and the CB contact 145, a sufficient thickness of dielectric material, referred to as the minimum dielectric distance, is provided therebetween. This dielectric separation distance is represented by the arrow 160. However, due to misalignment inherent when forming the via 150, the distance between the via 150 and the CB contact 145 may be less than the distance 160, as shown by the separation distance 165. To address the alignment variations, the product 100 is designed so that the distance 165 is greater than the minimum dielectric distance under worst case misalignment conditions. As a result, the distance between the CA contact 140 and the CB contact 145 in the design of the product 100 is increased, resulting in a decreased pattern density.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.